FIG. 1 is a circuit diagram showing a configuration of a conventional phase shifter disclosed in “2000 IEEE Microwave Theory and Technique Symposium Digest”, for example. In FIG. 1, reference numerals 1a and 1b each designate an input/output terminal; 2a and 2b each designate an FET; 3a, 3b and 3c each designate an inductor; 4a and 4c each designate a resistor; 5a and 5b each designate a control signal terminal; and the reference numeral 8 designates a capacitor.
Next, the operation will be described.
FIG. 2 is an equivalent circuit showing the operation of the conventional phase shifter.
First, consider a case where the control signal terminal 5a is supplied with a negative voltage that will pinch off the FET 2a, and the control signal terminal 5b is supplied with a zero or positive voltage that will bring the FET 2b into conduction. In this case, the phase shifter is represented by the equivalent circuit as shown in FIG. 2.
Here, if the sum of the OFF-state capacitance of the FET 2a and the capacitance of the capacitor 8 is very small, and the ON-state resistance of the FET 2b is small, the circuit operates as a π-type high-pass filter.
Next, consider a case where the control signal terminal 5a is supplied with a zero or positive voltage that will bring the FET 2a into conduction, and the control signal terminal 5b is supplied with a negative voltage that will pinch off the FET 2b. 
FIG. 3 is an equivalent circuit showing the operation of the conventional phase shifter. It shows an equivalent circuit of the phase shifter described above.
Here, if the ON-state resistance of the FET 2a is small, and if the OFF-state capacitance of the FET 2b and inductor 3c cause parallel resonance at a desired frequency, the inductors 3a and 3b have only a small effect. Thus, the circuit is equivalent to a through circuit.
Although the high-pass filter advances the phase, the through state little varies the pass phase. Accordingly, switching the control signals makes it possible to electrically switch the pass phase from the input/output terminal 1a to the input/output terminal 1b. 
With the foregoing configuration, the conventional phase shifter has a problem of its considerable loss because of the reduced gate width of the FET 2a, which is designed to curb the effect of the OFF-state capacitance of the FET 2a in the pinched-off state.
The present invention is implemented to solve the foregoing problem. Therefore an object of the present invention is to provide a compact and low-loss phase shifter and multiple-bit phase shifter.